Datasheet > 8430S803BYILFT

8430S803BYILFT

更新时间： 2022-02-26 13:44:41

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
30页	1046K
描述
Clock Generator for Cavium Processors

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8430S803BYILFT 数据手册

Clock Generator for Cavium Processors

ICS8430S803I

DATA SHEET

General Description

Features

The ICS8430S803I is a PLL-based clock generator specifically

designed for Cavium Networks SoC processors. This high

performance device is optimized to generate the processor core

reference clock, the DDR reference clocks, the PCI/PCI-X bus

clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.

The clock generator offers low-jitter, low-skew clock outputs, and

edge rates that easily meet the input requirements for the

CN30XX/CN31XX/CN38XX/CN58XX processors. The output

frequencies are generated from a 25MHz external input source or an

external 25MHz parallel resonant crystal. The extended temperature

range of the ICS8430S803I supports telecommunication,

networking, and storage requirements.

ꢀ One selectable differential output pair for DDR 533/400/667,

LVPECL, LVDS interface levels

ꢀ Nine LVCMOS/ LVTTL outputs, 23Ω typical output impedance

ꢀ Selectable external crystal or differential input source

ꢀ Crystal oscillator interface designed for 25MHz, parallel resonant

crystal

ꢀ Differential input pair (PCLK, nPCLK) accepts LVPECL, LVDS,

CML, input levels

ꢀ Internal resistor bias on nPCLK pin allows the user to drive PCLK

input with external single-ended (LVCMOS/ LVTTL) input levels

ꢀ Power supply modes:

CORE / OUTPUT

3.3V / 3.3V LVDS, LVPECL, LVCMOS

3.3V / 2.5V LVCMOS

ꢀ -40°C to 85°C ambient operating temperature

ꢀ Available in lead-free (RoHS 6) package

Applications

ꢀ Systems using Cavium Processors

ꢀ CPE Gateway Design

ꢀ Home Media Servers

ꢀ 802.11n AP or Gateway

ꢀ Soho Secure Gateway

ꢀ Soho SME Gateway

Pin Assignment

ꢀ Wireless Soho and SME VPN Solutions

ꢀ Wired and Wireless Network Security

ꢀ Web Servers and Exchange Servers

48 47 46 45 44 43 42 41 40 39 38 37

V_DD

V_{DDO_CD}

nOE_D

GND

QD0

nPLL_ SEL

QD1

ICS8430S803I

48-Pin TQFP,E-Pad

48 TQFP, E-Pad

7mm x 7mm x1mm

CORE_SEL

GND

XTAL

_IN

_ OUT

XTAL

7mm x 7mm x 1mm package

body

nXTAL

_ SEL

GND

package body

Y Package

Top View

PCLK

nOE_REF

V_{DDO_B}

QB0

nPCLK

nOE_C

Top View

nOE_B

GND

QB1

V_{DDO_B}

15 16 17 18 19 20 21 22 23

13 14

ICS8430S803BYI REVISION A MARCH 28, 2011

12 3 4 5 6 7...30

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