ICS8430S803I Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 13, 23
VDD
Power
Input
Core supply pins.
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
2
nOE_D
Pulldown
3, 12, 30, 31,
39, 42, 46
GND
Power
Input
Input
Power supply ground.
PLL bypass. When LOW, PLL is enabled. When HIGH, PLL is bypassed.
LVCMOS/LVTTL interface levels.
4
nPLL_SEL
Pulldown
5,
6
XTAL_IN,
XTAL_OUT
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Selects XTAL input when LOW. Selects differential clock (PCLK, nPCLK) input
when HIGH. LVCMOS/LVTTL interface levels.
7
8
9
nXTAL_SEL
PCLK
Input
Input
Input
Pulldown
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
nPCLK
Inverting differential clock input. Internal resistor bias to VDD/2.
Active LOW output enable for Bank C output. When logic HIGH, the output is high
impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL
interface levels.
10
nOE_C
Input
Input
Pulldown
Pulldown
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
11
14
nOE_B
nOE_A
Input
Input
Pulldown
Pulldown
Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
Selects the SPI PLL clock reference frequency. See Table 3D.
15,
16
SPI_SEL1,
SPI_SEL0
17,
18
PCI_SEL1,
PCI_SEL0
Selects the PCI, PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Input
Pulldown
Pulldown
19,
20
DDR_SEL1,
DDR_SEL0
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
21, 22
24
nQA, QA
VDDA
Output
Power
Power
Output
Differential output pair. Selectable between LVPECL and LVDS interface levels.
Analog supply pin.
25, 28
26, 27
VDDO_B
QB1, QB0
Bank B output supply pins. 3.3 V or 2.5V supply.
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.
Active LOW output enabled. When logic HIGH, the QREF[2:0] outputs are high
impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled.
LVCMOS/ LVTTL interface levels.
29
32
nOE_REF
Input
Input
Pulldown
Pulldown
Selects the processor core clock output frequency. The output frequency is 50MHz
when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL
interface levels.
CORE_SEL
33, 34
35
QD1, QD0
QC
Output
Output
Power
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.
Single-end Bank C output. LVCMOS/LVTTL interface levels.
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.
36
VDDO_CD
Pin descriptions continue on the next page.
ICS8430S803BYI REVISION A MARCH 28, 2011
3
©2011 Integrated Device Technology, Inc.
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