PRELIMINARY
ICS843101I-100
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVPECL
100MHZ FREQUENCY MARGINING SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• 100MHz nominal LVPECL output
The ICS843101I-100 is a low phase-noise
ICS
frequency margining synthesizer with fre-
quency margining capability and is a member of
the HiPerClockS™ family of high performance
clock solutions from ICS. In the default mode,
• Selectable crystal oscillator interface designed for 24MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended input
HiPerClockS™
• Output frequency can be varied in 2% steps from
nominal
the device nominally generates a 100MHz LVPECL output
clock signal from a 24MHz crystal input. There is also a
frequency margining mode available where the device can
be programmed, using the serial interface, to vary the
output frequency up or down from nominal in 2% steps.
The ICS843101I-100 is provided in a 16-pin TSSOP.
• VCO range: 540MHz - 680MHz
• RMS phase jitter @ 100MHz, using a 24MHz crystal
(1.875MHz - 20MHz): 0.55ps (typical)
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEE
S_LOAD
S_DATA
S_CLOCK
SEL
MODE
VCCO
Q
nQ
VEE
CLK
XTAL_OUT
XTAL_IN
Pulldown
CLK
1
0
Q
24MHz
Phase
Detector
÷ P
VCO
÷ N
540 - 680MHz
XTAL_IN
nQ
OE
VCCA
OSC
XTAL_OUT
SEL
VCC
Pulldown
÷ M
ICS843101I-100
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
Pulldown
S_CLOCK
S_DATA
S_LOAD
MODE
Pulldown
Pulldown
Pulldown
Serial Control
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843101AGI-100
www.icst.com/products/hiperclocks.html
REV.A OCTOBER 20, 2005
1