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8430AYI-61T PDF预览

8430AYI-61T

更新时间: 2024-11-11 14:23:35
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
21页 288K
描述
Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32

8430AYI-61T 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP, QFP32,.35SQ,32针数:32
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.18
Is Samacsys:NJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
湿度敏感等级:3端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:500 MHz封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:3.3 V
主时钟/晶体标称频率:27 MHz认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Clock Generators
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:7 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

8430AYI-61T 数据手册

 浏览型号8430AYI-61T的Datasheet PDF文件第2页浏览型号8430AYI-61T的Datasheet PDF文件第3页浏览型号8430AYI-61T的Datasheet PDF文件第4页浏览型号8430AYI-61T的Datasheet PDF文件第5页浏览型号8430AYI-61T的Datasheet PDF文件第6页浏览型号8430AYI-61T的Datasheet PDF文件第7页 
ICS8430I-61  
500MHZ, CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL  
LVPECL FREQUENCY SYNTHESIZER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8430I-61 is a general purpose, dual output Dual differential 3.3V or 2.5V LVPECL outputs  
Crystal-to-3.3V, 2.5V Differential LVPECL High Frequency  
Selectable crystal oscillator interface  
Synthesizer . The ICS8430I-61 has a selectable TEST_CLK  
or LVCMOS/LVTTL TEST_CLK  
or crystal inputs. The VCO operates at a frequency range  
of 250MHz to 500MHz. The VCO frequency is programmed  
in steps equal to the value of the input reference or  
crystal frequency. The VCO and output frequency can be  
programmed using the serial or parallel interfaces to the  
configuration logic. Frequency steps as small as 1MHz can  
be achieved using a 16MHz crystal or TEST_CLK.  
Output frequency range: 20.83MHz to 500MHz  
Crystal input frequency range: 14MHz to 27MHz  
VCO range: 250MHz to 500MHz  
Parallel or serial interface for programming counter  
and output dividers  
RMS period jitter: 6ps (maximum)  
Cycle-to-cycle jitter: 30ps (maximum)  
Supply voltage modes:  
VCC/VCCA/VCCO  
3.3/3.3/3.3  
3.3/3.3/2.5  
-40°C to 85°C ambient operating temperature  
Available in both standard and lead-free RoHS compliant  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCO_SEL  
XTAL_SEL  
TEST_CLK  
0
32 31 30 29 28 27 26 25  
XTAL_IN  
1
OSC  
M5  
M6  
M7  
M8  
N0  
N1  
N2  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
XTAL_OUT  
TEST_CLK  
XTAL_SEL  
VCCA  
XTAL_OUT  
÷ 16  
÷1  
ICS8430I-61  
÷1.5  
S_LOAD  
S_DATA  
S_CLOCK  
MR  
PLL  
÷2  
÷3  
PHASE DETECTOR  
÷4  
÷6  
0
1
VEE  
VCO  
÷8  
FOUT0  
nFOUT0  
FOUT1  
nFOUT1  
MR  
÷12  
9
10 11 12 13 14 15 16  
÷ M  
S_LOAD  
S_DATA  
S_CLOCK  
nP_LOAD  
CONFIGURATION  
INTERFACE  
LOGIC  
TEST  
32-Lead LQFP  
7mm x 7mm x 1.4mm package body  
M0:M8  
N0:N2  
Y Package  
Top View  
8430AYI-61  
www.idt.com  
REV. D JULY 27, 2010  
1

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