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8430AY-62T

更新时间： 2024-02-16 16:54:57

品牌	Logo	应用领域
艾迪悌 - IDT		晶体时钟发生器微控制器和处理器外围集成电路
页数	文件大小	规格书
23页	828K
描述
500MHz, Crystal-to-3.3V, 2.5V Differential LVPECL Frequency Synthesizer

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8430AY-62T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32	针数：	32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.43
Is Samacsys：	N	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	7 mm
湿度敏感等级：	3	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	500 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP32,.35SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	240	电源：	3.3 V
主时钟/晶体标称频率：	27 MHz	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Clock Generators
最大压摆率：	130 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	7 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

8430AY-62T 数据手册

ICS8430-62 Datasheet

500MHz CRYSTAL-TO-3.3V, 2.5V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Functional Description

NOTE: The functional description that follows describes operation

using a 16MHz crystal. Valid PLL loop divider values for different

crystal or input frequencies are defined in the Input Frequency

Characteristics, Table 5, NOTE 1.

The TEST output is LOW when operating in the parallel input mode.

The relationship between the VCO frequency, the crystal frequency

and the M divider is defined as follows:

fVCO = fXTAL x M

The ICS8430-62 features a fully integrated PLL and therefore

requires no external components for setting the loop bandwidth. A

parallel-resonant, fundamental crystal is used as the input to the

on-chip oscillator. The output of the oscillator is divided by 16 prior to

the phase detector. With a 16MHz crystal, this provides a 1MHz

reference frequency. The VCO of the PLL operates over a range of

250MHz to 500MHz. The output of the M divider is also applied to the

phase detector.

The M value and the required values of M0 through M8 are shown in

Table 3B, Programmable VCO Frequency Function Table. Valid M

values for which the PLL will achieve lock for a 16MHz reference are

defined as 250 ≤ M ≤ 500. The frequency out is defined as follows:

fout = fVCO = fXTAL x M

Serial operation occurs when nP_LOAD is HIGH and S_LOAD is

LOW. The shift register is loaded by sampling the S_DATA bits with

the rising edge of S_CLOCK. The contents of the shift register are

loaded into the M divider and N output divider when S_LOAD

transitions from LOW-to-HIGH. The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD. If

S_LOAD is held HIGH, data at the S_DATA input is passed directly to

the M divider and N output divider on each rising edge of S_CLOCK.

The serial mode can be used to program the M and N bits and test

bits T1 and T0. The internal registers T0 and T1 determine the state

of the TEST output as follows:

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too high

or too low), the PLL will not achieve lock. The output of the VCO is

scaled by a divider prior to being sent to each of the LVPECL output

buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS8430-62 support two input

modes to program the M divider and N output divider. The two input

operational modes are parallel and serial. Figure 1 shows the timing

diagram for each mode. In parallel mode, the nP_LOAD input is

initially LOW. The data on inputs M0 through M8 and N0 through N2

is passed directly to the M divider and N output divider. On the

LOW-to-HIGH transition of the nP_LOAD input, the data is latched

and the M divider remains loaded until the next LOW transition on

nP_LOAD or until a serial event occurs. As a result, the M and N bits

can be hard-wired to set the M divider and N output divider to a

specific default state that will automatically occur during power-up.

TEST Output

LOW

S_DATA, Shift Register Input

Output of M Divider

Do Not Use

SERIAL LOADING

S_CLOCK

T1 T0 N2 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

S_DATA

S_LOAD

nP_LOAD

PARALLEL LOADING

M, N

M0:M8, N0:N2

nP_LOAD

S_LOAD

Time

Figure 1. Parallel & Serial Load Operations

ICS8430AY-62 REVISION A JULY 2, 2009

123 4 5 6 7...23

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8430AY-71	IDT	Clock Generator, PQFP32	获取价格
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8430AYI-61	IDT	Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32	获取价格
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8430AYI-61LFT	IDT	LVPECL Frequeny Synthesizer	获取价格
8430AYI-61T	IDT	Clock Generator, 500MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32	获取价格

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