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74VHC595PW PDF预览

74VHC595PW

更新时间: 2024-11-22 11:09:47
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
20页 297K
描述
8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction

74VHC595PW 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.58
Is Samacsys:N计数方向:RIGHT
系列:AHC/VHC/H/U/VJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:SERIAL IN SERIAL OUT湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):20.1 ns座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:90 MHz
Base Number Matches:1

74VHC595PW 数据手册

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74VHC595; 74VHCT595  
8-bit serial-in/serial-out or parallel-out shift register with  
output latches  
Rev. 3 — 25 June 2020  
Product data sheet  
1. General description  
The 74VHC595; 74VHCT595 are high-speed Si-gate CMOS devices and are pin compatible with  
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.  
The 74VHC595; 74VHCT595 are 8-stage serial shift registers with a storage register and 3-state  
outputs. The shift registers have separate clocks.  
Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data  
in each register is transferred to the storage register on a positive-going transition of the storage  
register clock input (STCP). If both clocks are connected together, the shift register will always be  
one clock pulse ahead of the storage register.  
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is  
also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage  
register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output  
whenever the output enable input (OE) is LOW.  
2. Features and benefits  
Balanced propagation delays  
All inputs have Schmitt-trigger action  
Inputs accept voltages higher than VCC  
Input levels:  
For 74VHC595: CMOS level  
For 74VHCT595: TTL level  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Multiple package options  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Applications  
Serial-to-parallel data conversion  
Remote control holding register  
 
 
 

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