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74VHC595SJX PDF预览

74VHC595SJX

更新时间： 2024-11-20 23:13:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 86K
描述
8-Bit Shift Register with Output Latches

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中文翻译

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74VHC595SJX 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：SOP
包装说明：SOP, SOP16,.3针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：8.02
Is Samacsys：N计数方向：RIGHT
系列：AHC/VHCJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup：50000000 Hz湿度敏感等级：1
位数：8功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/5.5 V
传播延迟（tpd）：18.5 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：Shift Registers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：115 MHz
Base Number Matches：1

74VHC595SJX 数据手册

 浏览型号74VHC595SJX的Datasheet PDF文件第2页浏览型号74VHC595SJX的Datasheet PDF文件第3页浏览型号74VHC595SJX的Datasheet PDF文件第4页浏览型号74VHC595SJX的Datasheet PDF文件第5页浏览型号74VHC595SJX的Datasheet PDF文件第6页浏览型号74VHC595SJX的Datasheet PDF文件第7页 
August 1993  
Revised April 1999  
74VHC595  
8-Bit Shift Register with Output Latches  
An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
General Description  
The VHC595 is an advanced high-speed CMOS Shift Reg-  
ister fabricated with silicon gate CMOS technology. It  
achieves the high-speed operation similar to equivalent  
Bipolar Schottky TTL while maintaining the CMOS low  
power dissipation.  
This device contains an 8-bit serial-in, parallel-out shift reg-  
ister that feeds an 8-bit D-type storage register. The stor-  
age register has eight 3-STATE outputs. Separate clocks  
are provided for both the shift register and the storage reg-  
ister. The shift register has a direct-overriding clear, serial  
input, and serial output (standard) pins for cascading. Both  
the shift register and storage register use positive-edge  
triggered clocks. If both clocks are connected together, the  
shift register state will always be one clock pulse ahead of  
the storage register.  
Features  
■ High Speed: tPD = 5.4 ns (typ) at VCC = 5V  
■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C  
■ High noise immunity: VNIH = VNIL = 28% VCC (min)  
■ Power down protection is provided on all inputs  
■ Low noise: VOLP = 0.9V (typ)  
■ Pin and function compatible with 74HC595  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC595M  
74VHC595SJ  
74VHC595MTC  
74VHC595N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS011640.prf  
www.fairchildsemi.com  
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中文翻译

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74VHC595SJX 替代型号

型号 品牌 替代类型 描述 数据表
74VHC595SJ FAIRCHILD

完全替代

 8-Bit Shift Register with Output Latches
SN74AHC595NSRG4 TI

类似代替

 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS
SN74AHC595NSRE4 TI

类似代替

 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

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