Datasheet > 74VHC74_04

74VHC74_04

更新时间： 2024-11-09 04:48:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
14页	453K
描述
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

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中文翻译

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数据手册

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74VHC74_04 数据手册

74VHC74

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

■

HIGH SPEED:

= 170 MHz (TYP.) at V = 5V

MAX

■ LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

SOP

TSSOP

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8 mA (MIN)

Table 1: Order Codes

PACKAGE

■

BALANCED PROPAGATION DELAYS:

T & R

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOP

74VHC74MTR

74VHC74TTR

TSSOP

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

IMPROVED LATCH-UP IMMUNITY

CLR and PR are independent of the clock and

accomplished by a low setting on the appropriate

input.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74VHC74 is an advanced high-speed CMOS

DUAL D-TYPE FLIP FLOP WITH PRESET AND

CLEAR fabricated with sub-micron silicon gate

and double-layer metal wiring C MOS technology.

A signal on the D INPUT is transferred to the Q

OUTPUTS during the positive going transition of

the clock pulse.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/14

November 2004

12 3 4 5 6 7...14

中文翻译

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74VHC74_08	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
74VHC74FT	TOSHIBA	获取价格	Dual D-Type Flip-Flop, TSSOP14B
74VHC74M	STMICROELECTRONICS	获取价格	DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
74VHC74M	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
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74VHC74M	ONSEMI	获取价格	双 D 型触发器，带预置和清除
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74VHC74MTC	FAIRCHILD	获取价格	Dual D-Type Flip-Flop with Preset and Clear
74VHC74MTC	ROCHESTER	获取价格	AHC/VHC/H/U/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO