Datasheet > 74VHC74SJ_08

74VHC74SJ_08

更新时间： 2024-11-05 12:23:31

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
10页	304K
描述
Dual D-Type Flip-Flop with Preset and Clear

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数据手册

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74VHC74SJ_08 数据手册

February 2008

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

Features

General Description

■ High Speed: f

= 170MHz (typ.) at T = 25°C

The VHC74 is an advanced high speed CMOS Dual

D-Type Flip-Flop fabricated with silicon gate CMOS

technology. It achieves the high speed operation similar

to equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation. The signal level applied to

the D input is transferred to the Q output during the posi-

tive going transition of the CK pulse. CLR and PR are

independent of the CK and are accomplished by setting

the appropriate input LOW.

MAX

■ High noise immunity: V

= V

= 28% V (min.)

NIH

NIL CC

■ Power down protection is provided on all inputs

■ Low power dissipation: I = 2µA (max.) at T = 25°C

■ Pin and function compatible with 74HC74

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Package

Order Number

Number

Package Description

74VHC74M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC74SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC74MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC74N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

74VHC74 Rev. 1.3.0

www.fairchildsemi.com

12 3 4 5 6 7...10

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