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74LVC1G57GN PDF预览

74LVC1G57GN

更新时间: 2024-11-22 04:18:39
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
20页 224K
描述
SPECIALTY LOGIC CIRCUIT, PDSO6, 0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6

74LVC1G57GN 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SON包装说明:0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6
针数:6Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.65
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1 mm
逻辑集成电路类型:LOGIC CIRCUIT湿度敏感等级:1
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:0.35 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:PURE TIN
端子形式:NO LEAD端子节距:0.3 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:0.9 mmBase Number Matches:1

74LVC1G57GN 数据手册

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74LVC1G57  
Low-power configurable multiple function gate  
Rev. 7 — 10 September 2014  
Product data sheet  
1. General description  
The 74LVC1G57 provides configurable multiple functions. The output state is determined  
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,  
NOR, XNOR, inverter and buffer. All inputs can be connected to VCC or GND.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly  
changing input signals into sharply defined, jitter-free output signals.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C.  

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