Datasheet > 74LVC1G58_09

74LVC1G58_09

更新时间： 2024-11-18 06:31:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
18页	102K
描述
Low-power configurable multiple function gate

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74LVC1G58_09 数据手册

74LVC1G58

Low-power conﬁgurable multiple function gate

Rev. 04 — 27 April 2009

Product data sheet

1. General description

The 74LVC1G58 provides conﬁgurable multiple functions. The output state is determined

by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

NOR, XOR, inverter and buffer. All inputs can be connected to V_CCor GND.

The three inputs (A, B and C) are capable of transforming slowly changing input signals

into sharply deﬁned, jitter-free output signals.

The gate switches at different points for positive and negative-going signals. The

difference between the positive voltage V_T+and the negative voltage V_T−is deﬁned as the

hysteresis voltage V_H.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant input/output for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8B/JESD36 (2.7 V to 3.6 V).

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V.

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...18

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