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74LVC1G58GW-Q100 PDF预览

74LVC1G58GW-Q100

更新时间: 2024-11-19 11:13:55
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
14页 235K
描述
Low-power configurable multiple function gateProduction

74LVC1G58GW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SC-88, 6 PINReach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.42
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
逻辑集成电路类型:LOGIC CIRCUIT湿度敏感等级:1
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED筛选级别:AEC-Q100
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mm

74LVC1G58GW-Q100 数据手册

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74LVC1G58-Q100  
Low-power configurable multiple function gate  
Rev. 4 — 1 February 2022  
Product data sheet  
1. General description  
The 74LVC1G58-Q100 is a configurable multiple function gate with Schmitt-trigger inputs. The  
device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR,  
inverter and buffer; using the 3-bit input. All inputs can be connected diectly to VCC or GND. Inputs  
can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as  
translators in mixed 3.3 V and 5 V environments.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
±24 mA output drive (VCC = 3.0 V)  
CMOS low power dissipation  
IOFF circuitry provides partial Power-down mode operation  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Overvoltage tolerant inputs to 5.5 V  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC1G58GW-Q100 -40 °C to +125 °C  
TSSOP6  
plastic thin shrink small outline package;  
6 leads; body width 1.25 mm  
SOT363-2  
74LVC1G58GV-Q100 -40 °C to +125 °C  
SC-74;  
TSOP6  
plastic surface-mounted package; 6 leads  
SOT457  
 
 
 

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