Datasheet > 74LVC1G74_09

74LVC1G74_09

更新时间： 2024-09-19 06:31:55

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
21页	505K
描述
Single D-type flip-flop with set and reset; positive edge trigger

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74LVC1G74_09 数据手册

74LVC1G74

Single D-type ﬂip-ﬂop with set and reset; positive edge trigger

Rev. 08 — 3 December 2009

Product data sheet

1. General description

The 74LVC1G74 is a single positive edge triggered D-type ﬂip-ﬂop with individual data (D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing damaging backﬂow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant inputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I ±24 mA output drive (V_CC= 3.0 V)

I ESD protection:

N HBM JESD22-A114F exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...21

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