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74LVC1G58GW-Q100 PDF预览

74LVC1G58GW-Q100

更新时间: 2024-11-18 15:29:19
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
17页 126K
描述
IC SPECIALTY LOGIC CIRCUIT, Logic IC:Other

74LVC1G58GW-Q100 技术参数

生命周期:Transferred包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.65系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6长度:2 mm
逻辑集成电路类型:LOGIC CIRCUIT功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH筛选级别:AEC-Q100
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mmBase Number Matches:1

74LVC1G58GW-Q100 数据手册

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74LVC1G58-Q100  
Low-power configurable multiple function gate  
Rev. 1 — 10 June 2014  
Product data sheet  
1. General description  
The 74LVC1G58-Q100 provides configurable multiple functions. The output state is  
determined by eight patterns of 3-bit input. The user can choose the logic functions AND,  
OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly  
changing input signals into sharply defined, jitter-free output signals.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  

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