Datasheet > 74LVC1G57GN,132

74LVC1G57GN,132

更新时间： 2024-11-18 14:47:07

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管逻辑集成电路
页数	文件大小	规格书
20页	149K
描述
74LVC1G57 - Low-power configurable multiple function gate SON 6-Pin

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74LVC1G57GN,132 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SON
包装说明：	0.90 X 1 MM, 0.35 MM HEIGHT, SOT-1115, SON-6	针数：	6
Reach Compliance Code：	compliant	风险等级：	5.68
Is Samacsys：	N	Base Number Matches：	1

74LVC1G57GN,132 数据手册

74LVC1G57

Low-power configurable multiple function gate

Rev. 6 — 6 December 2011

Product data sheet

1. General description

The 74LVC1G57 provides configurable multiple functions. The output state is determined

by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,

NOR, XNOR, inverter and buffer. All inputs can be connected to V_CCor GND.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly

changing input signals into sharply defined, jitter-free output signals.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V).

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C.

12 3 4 5 6 7...20

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