ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢂ ꢉ
ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢍꢎ ꢏꢐ ꢋ ꢑꢄ ꢊꢐ ꢍꢑ ꢄꢒ ꢐ
ꢓ ꢊꢎ ꢔ ꢕꢀꢏ ꢁꢆꢔꢖ ꢒꢁ ꢒꢗꢀ ꢆ ꢄꢋ ꢕꢖ
SCES560A − MARCH 2004 − REVISED AUGUST 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1
2
3
6
5
4
CLK
GND
D
CLR
Inputs Accept Voltages to 5.5 V
V
CC
Max t of 4.3 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
24-mA Output Drive at 3.3 V
Q
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
3 4
2 5
1 6
D
GND
CLK
Q
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
V
CC
CLR
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single D-type flip-flop is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D)
is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G175YEPR
Reel of 3000
_ _ _D6_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SN74LVC1G175YZPR
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G175DBVR
SN74LVC1G175DBVT
SN74LVC1G175DCKR
SOT (SOT-23) − DBV
C75_
D6_
SOT (SC-70) − DCK
Reel of 250
SN74LVC1G175DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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ꢠ ꢟꢞ ꢙ ꢧꢞ ꢜ ꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢐꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟꢣ ꢠ ꢟ ꢘꢙ ꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟꢣ ꢜꢠ ꢨ
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