5秒后页面跳转
74LVC1G175GW-Q100 PDF预览

74LVC1G175GW-Q100

更新时间: 2024-11-06 20:10:07
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 117K
描述
IC D FLIP-FLOP, FF/Latch

74LVC1G175GW-Q100 技术参数

生命周期:Transferred包装说明:TSSOP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.58系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6长度:2 mm
逻辑集成电路类型:D FLIP-FLOP位数:1
功能数量:1端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟(tpd):17 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:1.25 mm最小 fmax:200 MHz
Base Number Matches:1

74LVC1G175GW-Q100 数据手册

 浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第2页浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第3页浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第4页浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第5页浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第6页浏览型号74LVC1G175GW-Q100的Datasheet PDF文件第7页 
74LVC1G175-Q100  
Single D-type flip-flop with reset; positive-edge trigger  
Rev. 1 — 15 November 2013  
Product data sheet  
1. General description  
The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type  
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q  
output. The master reset (MR) is an asynchronous active LOW input and operates  
independently of the clock input. Information on the data input is transferred to the  
Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable  
one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The  
inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial  
power-down applications using IOFF. The IOFF circuitry disables the output, preventing the  
damaging backflow current through the device when it is powered down. Schmitt trigger  
action at all inputs makes the circuit highly tolerant of slower input rise and fall times.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )  
 
 

与74LVC1G175GW-Q100相关器件

型号 品牌 获取价格 描述 数据表
74LVC1G175GW-Q100H NXP

获取价格

74LVC1G175-Q100 - Single D-type flip-flop with reset; positive-edge trigger TSSOP 6-Pin
74LVC1G175-Q100 NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge trigger
74LVC1G17FW4-7 DIODES

获取价格

SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17FZ4-7 DIODES

获取价格

SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17GF NXP

获取价格

Single Schmitt trigger buffer
74LVC1G17GM NXP

获取价格

Single Schmitt-trigger buffer
74LVC1G17GM NEXPERIA

获取价格

Single Schmitt trigger bufferProduction
74LVC1G17GM,132 NXP

获取价格

74LVC1G17 - Single Schmitt trigger buffer SON 6-Pin
74LVC1G17GM-Q100 NEXPERIA

获取价格

Single Schmitt trigger bufferProduction
74LVC1G17GN NXP

获取价格

Single Schmitt trigger buffer