Datasheet > 74LVC1G175GM

74LVC1G175GM

更新时间： 2024-11-07 11:11:39

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
17页	263K
描述
Single D-type flip-flop with reset; positive-edge triggerProduction

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74LVC1G175GM 数据手册

74LVC1G175

Single D-type flip-flop with reset; positive-edge trigger

Rev. 10 — 27 January 2022

Product data sheet

1. General description

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with

individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the

clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH

transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH

clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device

in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall

times.

2. Features and benefits

•

Wide supply voltage range from 1.65 V to 5.5 V

•

High noise immunity

Overvoltage tolerant inputs to 5.5 V

±24 mA output drive (V_CC= 3.0 V)

CMOS low power dissipation

Direct interface with TTL levels

I_OFFcircuitry provides partial Power-down mode operation

Latch-up performance exceeds 250 mA

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V.

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C.

12 3 4 5 6 7...17

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