5秒后页面跳转
74LVC1G175GF PDF预览

74LVC1G175GF

更新时间: 2024-11-06 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
17页 94K
描述
Single D-type flip-flop with reset; positive-edge trigger

74LVC1G175GF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SON
包装说明:VSON, SOLCC6,.04,14针数:6
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.3系列:LVC/LCX/Z
JESD-30 代码:S-PDSO-N6JESD-609代码:e3
长度:1 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:175000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:1功能数量:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装等效代码:SOLCC6,.04,14封装形状:SQUARE
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:0.5 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.35 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:1 mm
最小 fmax:200 MHzBase Number Matches:1

74LVC1G175GF 数据手册

 浏览型号74LVC1G175GF的Datasheet PDF文件第2页浏览型号74LVC1G175GF的Datasheet PDF文件第3页浏览型号74LVC1G175GF的Datasheet PDF文件第4页浏览型号74LVC1G175GF的Datasheet PDF文件第5页浏览型号74LVC1G175GF的Datasheet PDF文件第6页浏览型号74LVC1G175GF的Datasheet PDF文件第7页 
74LVC1G175  
Single D-type flip-flop with reset; positive-edge trigger  
Rev. 03 — 21 May 2007  
Product data sheet  
1. General description  
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type  
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q  
output.  
The master reset (MR) is an asynchronous active LOW input and operates independently  
of the clock input. Information on the data input is transferred to the Q output on the  
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time  
prior to the LOW-to-HIGH clock transition for predictable operation.  
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
this device in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and  
fall times.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant inputs for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8B/JESD36 (2.7 V to 3.6 V).  
±24 mA output drive (VCC = 3.0 V)  
ESD protection:  
HBM JESD22-A114E exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V.  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C.  

与74LVC1G175GF相关器件

型号 品牌 获取价格 描述 数据表
74LVC1G175GM NXP

获取价格

Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GM NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge triggerProduction
74LVC1G175GN NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge triggerProduction
74LVC1G175GS NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge triggerProduction
74LVC1G175GV NXP

获取价格

Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GV NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge triggerProduction
74LVC1G175GV,125 NXP

获取价格

74LVC1G175 - Single D-type flip-flop with reset; positive edge trigger TSOP 6-Pin
74LVC1G175GV-Q100 NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge trigger
74LVC1G175GV-Q100H NXP

获取价格

74LVC1G175-Q100 - Single D-type flip-flop with reset; positive-edge trigger TSOP 6-Pin
74LVC1G175GW NEXPERIA

获取价格

Single D-type flip-flop with reset; positive-edge triggerProduction