Datasheet > 74LVC1G175-Q100

74LVC1G175-Q100

更新时间： 2024-11-07 01:16:03

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
13页	221K
描述
Single D-type flip-flop with reset; positive-edge trigger

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LVC1G175-Q100 数据手册

74LVC1G175-Q100

Single D-type flip-flop with reset; positive-edge trigger

Rev. 3 — 3 October 2019

Product data sheet

1. General description

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop

with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master

reset (MR) is an asynchronous active LOW input and operates independently of the clock input.

Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the

clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition

for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature

allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for

partial power-down applications using I_OFF. The I_OFFcircuitry disables the output, preventing the

damaging backflow current through the device when it is powered down. Schmitt trigger action at

all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8B/JESD36 (2.7 V to 3.6 V).

•

±24 mA output drive (V_CC= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

SOT363

SOT457

74LVC1G175GW-Q100 -40 °C to +125 °C

74LVC1G175GV-Q100 -40 °C to +125 °C

SC-88

SC-74

plastic surface-mounted package; 6 leads

plastic surface-mounted package

(SC-74; TSOP6); 6 leads

12 3 4 5 6 7...13

中文翻译

下载PDF

与74LVC1G175-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC1G17FW4-7	DIODES	获取价格	SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17FZ4-7	DIODES	获取价格	SINGLE SCHMITT-TRIGGER BUFFER
74LVC1G17GF	NXP	获取价格	Single Schmitt trigger buffer
74LVC1G17GM	NXP	获取价格	Single Schmitt-trigger buffer
74LVC1G17GM	NEXPERIA	获取价格	Single Schmitt trigger bufferProduction
74LVC1G17GM,132	NXP	获取价格	74LVC1G17 - Single Schmitt trigger buffer SON 6-Pin
74LVC1G17GM-Q100	NEXPERIA	获取价格	Single Schmitt trigger bufferProduction
74LVC1G17GN	NXP	获取价格	Single Schmitt trigger buffer
74LVC1G17GN	NEXPERIA	获取价格	Single Schmitt trigger bufferProduction
74LVC1G17GS	NXP	获取价格	Single Schmitt trigger buffer

与74LVC1G175-Q100相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVC1G175-Q100

74LVC1G175-Q100 数据手册

与74LVC1G175-Q100相关器件

与74LVC1G175-Q100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVC1G175-Q100

74LVC1G175-Q100 数据手册

与74LVC1G175-Q100相关器件

与74LVC1G175-Q100相关文章

您还可以找

您在本页遇到什么问题？