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74LV132D,132 PDF预览

74LV132D,132

更新时间: 2024-11-18 14:50:11
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
17页 199K
描述
NAND Gate, LV/LV-A/LVX/H Series, 4-Func, 2-Input, CMOS, PDSO14

74LV132D,132 技术参数

生命周期:Active包装说明:SOP,
Reach Compliance Code:unknown风险等级:5.58
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
长度:8.65 mm逻辑集成电路类型:NAND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE传播延迟(tpd):43 ns
座面最大高度:1.75 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

74LV132D,132 数据手册

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74LV132  
Quad 2-input NAND Schmitt trigger  
Rev. 6 — 9 December 2015  
Product data sheet  
1. General description  
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible  
with 74HC132 and 74HCT132.  
The 74LV132 contains four 2-input NAND gates which accept standard input signals.  
They are capable of transforming slowly changing input signals into sharply defined,  
jitter-free output signals.  
The gate switches at different points for positive and negative-going signals. The  
difference between the positive voltage VT+ and the negative voltage VTis defined as the  
input hysteresis voltage VH.  
2. Features and benefits  
Wide operating voltage: 1.0 V to 5.5 V  
Optimized for low voltage applications: 1.0 V to 3.6 V  
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C  
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 C  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from 40 C to +85 C and from 40 C to +125 C  
3. Applications  
Wave and pulse shapers for highly noisy environments  
Astable multivibrators  
Monostable multivibrators  

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