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74LV132N,112 PDF预览

74LV132N,112

更新时间: 2024-11-18 21:19:03
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 109K
描述
74LV132N

74LV132N,112 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.58
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDIP-T14
JESD-609代码:e4长度:19.025 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.006 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:25 ns传播延迟(tpd):43 ns
认证状态:Not Qualified施密特触发器:YES
座面最大高度:4.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.62 mm
Base Number Matches:1

74LV132N,112 数据手册

 浏览型号74LV132N,112的Datasheet PDF文件第2页浏览型号74LV132N,112的Datasheet PDF文件第3页浏览型号74LV132N,112的Datasheet PDF文件第4页浏览型号74LV132N,112的Datasheet PDF文件第5页浏览型号74LV132N,112的Datasheet PDF文件第6页浏览型号74LV132N,112的Datasheet PDF文件第7页 
74LV132  
Quad 2-input NAND Schmitt trigger  
Rev. 05 — 2 July 2009  
Product data sheet  
1. General description  
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible  
with 74HC132 and 74HCT132.  
The 74LV132 contains four 2-input NAND gates which accept standard input signals.  
They are capable of transforming slowly changing input signals into sharply defined,  
jitter-free output signals.  
The gate switches at different points for positive and negative-going signals. The  
difference between the positive voltage VT+ and the negative voltage VTis defined as the  
input hysteresis voltage VH.  
2. Features  
I Wide operating voltage: 1.0 V to 5.5 V  
I Optimized for low voltage applications: 1.0 V to 3.6 V  
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and  
Tamb = 25 °C  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
I Wave and pulse shapers for highly noisy environments  
I Astable multivibrators  
I Monostable multivibrators  
 
 
 

74LV132N,112 替代型号

型号 品牌 替代类型 描述 数据表
74LV132N NXP

完全替代

Quad 2-input NAND Schmitt-trigger
SN74AHC132NE4 TI

功能相似

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS

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