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74AUP2G00DC

更新时间： 2024-01-31 10:12:13

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	84K
描述
Low-power dual 2-input NAND gate

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中文翻译

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数据手册

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74AUP2G00DC 数据手册

74AUP2G00

Philips Semiconductors

Low-power dual 2-input NAND gate

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ^[1]Max

Min

Max

(85 °C) (125 °C)

C_L= 5 pF, 10 pF, 15 pF and 30 pF

C_PDpower dissipation f_i= 1 MHz;

capacitance V_I= GND to V_CC

[3]

V_CC= 0.8 V

2.8

2.9

3.0

3.4

3.9

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din µW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

12. Waveforms

nA, nB input

PHL

PLH

nY output

mna213

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage drop that occur with the output load.

Fig 7. The data input (nA or nB) to output (nY) propagation delays

Table 9.

Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

0.8 V to 3.6 V

0.5 × V_CC

V_CC

≤ 3.0 ns

74AUP2G00_1

Product data sheet

Rev. 01 — 25 August 2006

9 of 16

1...6 7 8910 11 12...16

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