Datasheet > 74AUP2G00GT

74AUP2G00GT

更新时间： 2024-11-20 11:12:31

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
20页	297K
描述
Low-power dual 2-input NAND gateProduction

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74AUP2G00GT 数据手册

74AUP2G00

Low-power dual 2-input NAND gate

Rev. 12 — 14 July 2023

Product data sheet

1. General description

The 74AUP2G00 provides dual 2-input NAND function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times

across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CCrange

from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing a damaging backflow current through the device when it is powered

down.

2. Features and benefits

•

Wide supply voltage range from 0.8 V to 3.6 V

•

High noise immunity

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

•

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

ESD protection:

•

HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...20

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