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74AUP2G00DC

更新时间： 2024-01-21 01:48:08

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	84K
描述
Low-power dual 2-input NAND gate

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74AUP2G00DC 数据手册

74AUP2G00

Philips Semiconductors

Low-power dual 2-input NAND gate

11. Dynamic characteristics

Table 8.

Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.

Symbol Parameter

Conditions

25 °C

−40 °C to +125 °C

Unit

Min Typ^[1]Max

Min

Max

(85 °C) (125 °C)

C_L= 5 pF

[2]

t_pd

propagation delay nA, nB to nY; see Figure 7

V_CC= 0.8 V

17.5

5.3

3.8

3.1

2.5

2.2

V_CC= 1.1 V to 1.3 V

2.5

2.0

1.6

1.3

1.0

11.0

6.8

5.3

4.0

3.6

2.1

1.8

1.4

1.1

1.0

12.2

7.8

6.2

4.7

4.2

13.5

8.6

6.9

5.2

4.7

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

C_L= 10 pF

t_pd

propagation delay nA, nB to nY; see Figure 7

V_CC= 0.8 V

21.0

6.1

4.4

3.7

3.0

2.8

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

2.4

2.0

1.4

1.3

13.0

7.9

6.2

4.7

4.3

2.2

1.9

1.3

1.2

14.4

9.2

7.3

5.6

4.9

15.9

10.2

8.1

6.2

5.4

C_L= 15 pF

t_pd

propagation delay nA, nB to nY; see Figure 7

V_CC= 0.8 V

24.5

6.9

5.0

4.1

3.5

3.2

V_CC= 1.1 V to 1.3 V

3.4

2.8

2.0

1.7

1.6

14.8

8.9

7.0

5.3

4.9

3.1

2.5

2.0

1.5

1.4

16.5

10.5

8.3

18.2

11.6

9.2

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

6.4

7.1

V_CC= 3.0 V to 3.6 V

5.7

6.3

C_L= 30 pF

t_pd

propagation delay nA, nB to nY; see Figure 7

V_CC= 0.8 V

34.8

9.2

6.5

5.4

4.6

4.3

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

4.6

3.0

2.6

2.4

2.3

20.1

11.8

9.3

4.1

2.9

2.3

2.1

22.6

14.0

11.1

8.5

24.9

15.4

12.3

9.4

7.1

6.5

7.6

8.4

74AUP2G00_1

Product data sheet

Rev. 01 — 25 August 2006

8 of 16

1...5 6 789 10 11...16

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