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74AUP2G00DC

更新时间： 2024-02-16 05:10:50

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	84K
描述
Low-power dual 2-input NAND gate

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中文翻译

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数据手册

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74AUP2G00DC 数据手册

74AUP2G00

Philips Semiconductors

Low-power dual 2-input NAND gate

EXT

5 kΩ

PULSE

GENERATOR

DUT

001aac521

Test data is given in Table 10.

Deﬁnitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 8. Load circuitry for switching times

Table 10. Test data

Supply voltage

V_CC

Load

C_L

V_EXT

[1]

R_L

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ

GND

2 × V_CC

[1] For measuring enable and disable times R_L= 5 kΩ, for measuring propagation delays, setup and hold times and pulse width R_L= 1 MΩ.

74AUP2G00_1

Product data sheet

Rev. 01 — 25 August 2006

10 of 16

1...7 8 91011 12 13...16

中文翻译

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