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74AUP2G00DC

更新时间： 2024-02-21 13:30:59

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	84K
描述
Low-power dual 2-input NAND gate

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74AUP2G00DC 数据手册

74AUP2G00

Philips Semiconductors

Low-power dual 2-input NAND gate

8. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

I_IK

Parameter

Conditions

Min

Max

+4.6

−50

Unit

supply voltage

−0.5

input clamping current

input voltage

V_I< 0 V

[1]

V_I

−0.5

+4.6

−50

I_OK

output clamping current

output voltage

V_O< 0 V

V_O

Active mode and Power-down mode

V_O= 0 V to V_CC

−0.5

+4.6

±20

I_O

output current

°C

I_CC

supply current

+50

−50

I_GND

T_stg

P_tot

ground current

storage temperature

total power dissipation

−65

+150

250

[2]

T_amb= −40 °C to +125 °C

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For VSSOP8 packages: above 110 °C the value of P_totderates linearly with 8.0 mW/K.

For XSON8 and XQFN8 packages: above 45 °C the value of P_totderates linearly with 2.4 mW/K.

9. Recommended operating conditions

Table 6.

Symbol

V_CC

Recommended operating conditions

Parameter

Conditions

Min

0.8

Max

3.6

Unit

supply voltage

input voltage

output voltage

V_I

3.6

V_O

Active mode

V_CC

3.6

Power-down mode; V_CC= 0 V

T_amb

ambient temperature

−40

+125

200

°C

ns/V

∆t/∆V

input transition rise and fall rate V_CC= 0.8 V to 3.6 V

74AUP2G00_1

Product data sheet

Rev. 01 — 25 August 2006

4 of 16

1 2 345 6 7...16

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