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74AUP2G00DC

更新时间： 2024-01-03 12:04:34

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	84K
描述
Low-power dual 2-input NAND gate

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数据手册

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74AUP2G00DC 数据手册

74AUP2G00

Philips Semiconductors

Low-power dual 2-input NAND gate

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74AUP2G00DC

74AUP2G00GT

74AUP2G00GM

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads; SOT765-1

body width 2.3 mm

XSON8

XQFN8

plastic extremely thin small outline package; no leads; SOT833-1

8 terminals; body 1 × 1.95 × 0.5 mm

plastic extremely thin quad ﬂat package; no leads; 8

SOT902-1

terminals; body 1.6 × 1.6 × 0.5 mm

4. Marking

Table 2.

Marking

Type number

Marking code

74AUP2G00DC

74AUP2G00GT

74AUP2G00GM

p00

5. Functional diagram

mna712

mna099

mna713

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

74AUP2G00

GND

001aae362

Fig 4. Pin conﬁguration SOT765-1 (VSSOP8)

74AUP2G00_1

Product data sheet

Rev. 01 — 25 August 2006

2 of 16

123 4 5 6 7...16

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