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74AHCT374PW-T PDF预览

74AHCT374PW-T

更新时间: 2024-09-19 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
17页 87K
描述
IC AHCT/VHCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 4.40 MM, PLASTIC, SOT-360-1, TSSOP-20, Bus Driver/Transceiver

74AHCT374PW-T 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.12系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:6.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:75000000 Hz
最大I(ol):0.008 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:13 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

74AHCT374PW-T 数据手册

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74AHC374; 74AHCT374  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 03 — 12 June 2008  
Product data sheet  
1. General description  
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type  
inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input  
(CP) and an output enable input (OE) are common to all flip-flops.  
The eight flip-flops will store the state of their individual D inputs that meet the set-up and  
hold times requirements for the LOW-to-HIGH CP transition.  
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is  
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Common 3-state output enable input  
I Input levels:  
N For 74AHC374: CMOS level  
N For 74AHCT374: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

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