Datasheet > 74AHCT377D-Q100J

74AHCT377D-Q100J

更新时间： 2024-12-01 14:47:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	167K
描述
74AHC(T)377-Q100 - Octal D-type flip-flop with data enable; positive-edge trigger SOP 20-Pin

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74AHCT377D-Q100J 技术参数

生命周期：	Transferred	零件包装代码：	SOP
包装说明：	7.50 MM, PLASTIC, MS-013, SOT163-1, SOP-20	针数：	20
Reach Compliance Code：	unknown	风险等级：	5.75
Is Samacsys：	N	Base Number Matches：	1

74AHCT377D-Q100J 数据手册

74AHC377-Q100;

74AHCT377-Q100

Octal D-type flip-flop with data enable; positive-edge trigger

Rev. 1 — 3 December 2013

Product data sheet

1. General description

The 74AHC377-Q100; 74AHCT377-Q100 is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A. The 74AHC377-Q100; 74AHCT377-Q100 has eight

edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock

input (CP) loads all flip-flops simultaneously when the data enable input (E) is LOW. The

state of each D input, one set-up time before the LOW-to-HIGH clock transition, is

transferred to the corresponding output (Qn) of the flip-flop. The E input is only required to

be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Balanced propagation delays

 All inputs have Schmitt-trigger actions

 Inputs accept voltages higher than V_CC

 Ideal for addressable register applications

 Data enable for address and data synchronization

 Eight positive-edge triggered D-type flip-flops

 Input levels:

 For 74AHC377-Q100: CMOS level

 For 74AHCT377-Q100: TTL level

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...17

中文翻译

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与74AHCT377D-Q100J相关器件

型号	品牌	获取价格	描述	数据表
74AHCT377D-T	NXP	获取价格	暂无描述
74AHCT377E	IDT	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, CDFP20
74AHCT377L	IDT	获取价格	D Flip-Flop, 8-Func, Positive Edge Triggered, CMOS, CQCC20
74AHCT377PW	NXP	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHCT377PW,112	NXP	获取价格	74AHC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger TSSOP2 20-Pin
74AHCT377PW,118	NXP	获取价格	74AHC(T)377 - Octal D-type flip-flop with data enable; positive-edge trigger TSSOP2 20-Pin
74AHCT377PW-Q100	NXP	获取价格	IC D FLIP-FLOP, FF/Latch
74AHCT377PW-Q100	NEXPERIA	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger
74AHCT377PW-T	NXP	获取价格	IC AHCT/VHCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, TS
74AHCT377-Q100	NEXPERIA	获取价格	Octal D-type flip-flop with data enable; positive-edge trigger

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