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74AHCT377D-T PDF预览

74AHCT377D-T

更新时间: 2024-12-01 13:04:55
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恩智浦 - NXP /
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16页 94K
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74AHCT377D-T 数据手册

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74AHC377; 74AHCT377  
Octal D-type flip-flop with data enable; positive-edge trigger  
Rev. 02 — 12 June 2008  
Product data sheet  
1. General description  
The 74AHC377; 74AHCT377 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC377; 74AHCT377 has eight edge-triggered, D-type flip-flops with individual D  
inputs and Q outputs. A common clock input (CP) loads all flip-flops simultaneously when  
the data enable input (E) is LOW. The state of each D input, one set-up time before the  
LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the  
flip-flop. The E input is only required to be stable one set-up time prior to the  
LOW-to-HIGH transition for predictable operation.  
For versions associated with the 74AHC377; 74AHCT377, refer to the following:  
For the master reset version, see 74AHC273; 74AHCT273  
For the transparent latch version, see 74AHC373; 74AHCT373  
For the 3-state version, see 74AHC374; 74AHCT374  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Ideal for addressable register applications  
I Data enable for address and data synchronization  
I Eight positive-edge triggered D-type flip-flops  
I Input levels:  
N For 74AHC377: CMOS level  
N For 74AHCT377: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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