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74AHCT374-Q100 PDF预览

74AHCT374-Q100

更新时间: 2024-12-02 01:06:31
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
18页 815K
描述
Octal D-type flip-flop; positive edge-trigger; 3-state

74AHCT374-Q100 数据手册

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74AHC374-Q100;  
74AHCT374-Q100  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 1 — 11 March 2014  
Product data sheet  
1. General description  
The 74AHC374-Q100; 74AHCT374-Q100 is a high-speed Si-gate CMOS device and is  
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with  
JEDEC standard No. 7-A.  
The 74AHC374-Q100; 74AHCT374-Q100 comprises eight D-type flip-flops featuring  
separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.  
A clock input (CP) and an output enable input (OE) are common to all flip-flops.  
The eight flip-flops will store the state of their individual D inputs that meet the set-up and  
hold times requirements for the LOW-to-HIGH CP transition.  
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is  
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
This product has been qualified to the Automotive Electronics Council (AEC) standard  
Q100 (Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from 40 C to +85 C and from 40 C to +125 C  
Balanced propagation delays  
All inputs have Schmitt-trigger actions  
Inputs accept voltages higher than VCC  
Common 3-state output enable input  
Input levels:  
For 74AHC374-Q100: CMOS level  
For 74AHCT374-Q100: TTL level  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  
Multiple package options  

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