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74AHCT374D,118 PDF预览

74AHCT374D,118

更新时间: 2024-11-04 15:26:35
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
17页 87K
描述
74AHC(T)374 - Octal D-type flip-flop; positive edge-trigger; 3-state SOP 20-Pin

74AHCT374D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.18
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:75000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

74AHCT374D,118 数据手册

 浏览型号74AHCT374D,118的Datasheet PDF文件第2页浏览型号74AHCT374D,118的Datasheet PDF文件第3页浏览型号74AHCT374D,118的Datasheet PDF文件第4页浏览型号74AHCT374D,118的Datasheet PDF文件第5页浏览型号74AHCT374D,118的Datasheet PDF文件第6页浏览型号74AHCT374D,118的Datasheet PDF文件第7页 
74AHC374; 74AHCT374  
Octal D-type flip-flop; positive edge-trigger; 3-state  
Rev. 03 — 12 June 2008  
Product data sheet  
1. General description  
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type  
inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input  
(CP) and an output enable input (OE) are common to all flip-flops.  
The eight flip-flops will store the state of their individual D inputs that meet the set-up and  
hold times requirements for the LOW-to-HIGH CP transition.  
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is  
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does  
not affect the state of the flip-flops.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Common 3-state output enable input  
I Input levels:  
N For 74AHC374: CMOS level  
N For 74AHCT374: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
 
 

74AHCT374D,118 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT374DWRG4 TI

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