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74AHC595D,118 PDF预览

74AHC595D,118

更新时间: 2024-11-06 14:47:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
21页 110K
描述
74AHC(T)595 - 8-bit serial-in/serial-out or parallel-out shift register SOP 16-Pin

74AHC595D,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:SOP包装说明:3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.4
计数方向:RIGHT系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:90000000 Hz湿度敏感等级:1
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2/5.5 V
传播延迟(tpd):20.1 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:90 MHz
Base Number Matches:1

74AHC595D,118 数据手册

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74AHC595; 74AHCT595  
8-bit serial-in/serial-out or parallel-out shift register with  
output latches; 3-state  
Rev. 03 — 25 April 2008  
Product data sheet  
1. General description  
The 74AHC595; 74AHCT595 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7A.  
The 74AHC595; 74AHCT595 is an 8-stage serial shift register with a storage register and  
3-state outputs. The shift register has separate clocks.  
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).  
The data in each register is transferred to the storage register on a positive-going  
transition of the storage register clock input (STCP). If both clocks are connected together,  
the shift register will always be one clock pulse ahead of the storage register.  
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.  
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The  
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register  
appears at the output whenever the output enable input (OE) is LOW.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC595: CMOS level  
N For 74AHCT595: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
I Serial-to-parallel data conversion  
I Remote control holding register  
 
 
 

74AHC595D,118 替代型号

型号 品牌 替代类型 描述 数据表
74AHC595BQ,115 NXP

完全替代

74AHC(T)595 - 8-bit serial-in/serial-out or parallel-out shift register QFN 16-Pin
74AHC595BQ-Q100,11 NXP

完全替代

74AHC(T)595-Q100 - 8-bit serial-in/serial-out or parallel-out shift register with output l

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