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74AHC74BQ PDF预览

74AHC74BQ

更新时间: 2024-11-06 12:50:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
18页 110K
描述
Dual D-type flip-flop with set and reset; positive-edge trigger

74AHC74BQ 数据手册

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74AHC74; 74AHCT74  
Dual D-type flip-flop with set and reset; positive-edge trigger  
Rev. 05 — 9 June 2008  
Product data sheet  
1. General description  
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible  
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard  
No. 7-A.  
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual  
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has  
complementary outputs (Q and Q).  
The set and reset are asynchronous active LOW inputs that operate independent of the  
clock input. Information on the data input is transferred to the Q output on the LOW to  
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to  
the LOW to HIGH clock transition for predictable operation.  
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock  
rise and fall times.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger actions  
I Inputs accept voltages higher than VCC  
I Input levels:  
N For 74AHC74: CMOS level  
N For 74AHCT74: TTL level  
I ESD protection:  
N HBM EIA/JESD22-A114E exceeds 2000 V  
N MM EIA/JESD22-A115-A exceeds 200 V  
N CDM EIA/JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  

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