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74AHC595BQ PDF预览

74AHC595BQ

更新时间: 2024-11-06 08:02:59
品牌 Logo 应用领域
恩智浦 - NXP 晶体移位寄存器触发器锁存器逻辑集成电路晶体管
页数 文件大小 规格书
21页 120K
描述
NPN general-purpose double transistors output latches; 3-state

74AHC595BQ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFN
包装说明:2.50 X 3.50 MM, 0.85 MM HEIGHT, PLASTIC, MO-241, SOT763-1, DHVQFN-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
计数方向:RIGHT系列:AHC/VHC/H/U/V
JESD-30 代码:R-PQCC-N16JESD-609代码:e4
长度:3.5 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
湿度敏感等级:1位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC16,.1X.14,20封装形状:RECTANGULAR
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:5 V传播延迟(tpd):20.1 ns
认证状态:Not Qualified座面最大高度:1 mm
子类别:Shift Registers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:NICKEL PALLADIUM GOLD
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:2.5 mm
最小 fmax:90 MHzBase Number Matches:1

74AHC595BQ 数据手册

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74AHC595; 74AHCT595  
8-bit serial-in/serial-out or parallel-out shift register with  
output latches; 3-state  
Rev. 04 — 11 August 2009  
Product data sheet  
1. General description  
The 74AHC595; 74AHCT595 are high-speed Si-gate CMOS devices and are pin  
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with  
JEDEC standard No. 7A.  
The 74AHC595; 74AHCT595 are 8-stage serial shift registers with a storage register and  
3-state outputs. The registers have separate clocks.  
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).  
The data in each register is transferred to the storage register on a positive-going  
transition of the storage register clock input (STCP). If both clocks are connected together,  
the shift register will always be one clock pulse ahead of the storage register.  
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.  
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The  
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register  
appears at the output whenever the output enable input (OE) is LOW.  
2. Features  
I Balanced propagation delays  
I All inputs have Schmitt-trigger action  
I Inputs accept voltages higher than VCC  
I Input levels:  
N The 74AHC595 operates with CMOS input levels  
N The 74AHCT595 operates with TTL input levels  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
N CDM JESD22-C101C exceeds 1000 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C  
3. Applications  
I Serial-to-parallel data conversion  
I Remote control holding register  

74AHC595BQ 替代型号

型号 品牌 替代类型 描述 数据表
74AHC595BQ NEXPERIA

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