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71V67603S133PF PDF预览

71V67603S133PF

更新时间: 2024-11-19 14:40:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 512K
描述
Cache SRAM, 256KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

71V67603S133PF 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991HTS代码:8542.32.00.41
风险等级:5.21Is Samacsys:N
最长访问时间:4.2 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:9437184 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.05 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.26 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

71V67603S133PF 数据手册

 浏览型号71V67603S133PF的Datasheet PDF文件第2页浏览型号71V67603S133PF的Datasheet PDF文件第3页浏览型号71V67603S133PF的Datasheet PDF文件第4页浏览型号71V67603S133PF的Datasheet PDF文件第5页浏览型号71V67603S133PF的Datasheet PDF文件第6页浏览型号71V67603S133PF的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
3.3V I/O, Burst Counter  
IDT71V67603  
IDT71V67803  
PipelinedOutputs,SingleCycleDeselect  
Features  
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,  
data, address and control registers. Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
theendofthewritecycle.  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBOinputpin.  
write enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-  
pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165  
fine pitchballgridarray(fBGA).  
Description  
The IDT71V67603/7803 are high-speed SRAMs organized as  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
N/A  
5310 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67802.  
APRIL 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5310/05  

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