Datasheet > 71V67603S150BGG8

71V67603S150BGG8

更新时间： 2024-11-20 06:19:39

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
23页	517K
描述
PBGA-119, Reel

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中文翻译

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71V67603S150BGG8 数据手册

256K X 36, 512K X 18

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

IDT71V67603

IDT71V67803

PipelinedOutputs,SingleCycleDeselect

Features

256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,

data, address and control registers. Internal logic allows the SRAM to

generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil

theendofthewritecycle.

◆

256K x 36, 512K x 18 memory configurations

◆

Supports high system speed:

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof

dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

orderofthesethreeaddressesaredefinedbytheinternalburstcounter

andthe LBO inputpin.

◆

LBO input selects interleaved or linear burst mode

◆

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

◆

3.3V core power supply

◆

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

◆

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-

pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165

fine pitchballgridarray(fBGA).

Description

The IDT71V67603/7803 are high-speed SRAMs organized as

PinDescriptionSummary

A⁰-A¹⁸

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CS⁰, CS1

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

(1)

BW¹, BW², BW³, BW4

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

ADV

ADSC

ADSP

LBO

Asynchronous

Synchronous

N/A

I/O⁰-I/O³¹, I/O^P1-I/O^P4

V^DD, V^DDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

V^SS

N/A

5310 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V67802.

FEBRUARY 2009

SEPTEMBER 2004

DSC-5310/06

12 3 4 5 6 7...23

中文翻译

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与71V67603S150BGG8相关器件

型号	品牌	获取价格	描述	数据表
71V67603S150BGGI8	IDT	获取价格	PBGA-119, Reel
71V67603S150BGI	IDT	获取价格	PBGA-119, Tray
71V67603S150BQ	IDT	获取价格	CABGA-165, Tray
71V67603S150BQI	IDT	获取价格	CABGA-165, Tray
71V67603S150BQI8	IDT	获取价格	CABGA-165, Reel
71V67603S150PF	ROCHESTER	获取价格	256KX36 CACHE SRAM, 3.8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V67603S150PF8	IDT	获取价格	Cache SRAM, 256KX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V67603S150PFG	ROCHESTER	获取价格	256KX36 STANDARD SRAM, 3.8ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC
71V67603S150PFG8	IDT	获取价格	TQFP-100, Reel
71V67603S150PFGI8	IDT	获取价格	TQFP-100, Reel

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