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71V67603S150BGI PDF预览

71V67603S150BGI

更新时间: 2024-09-20 10:00:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
23页 424K
描述
PBGA-119, Tray

71V67603S150BGI 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Active零件包装代码:PBGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.15
Is Samacsys:N最长访问时间:3.8 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):150 MHz
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:9437184 bit内存集成电路类型:CACHE SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:119
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
座面最大高度:2.36 mm最大待机电流:0.07 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.325 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn63Pb37)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

71V67603S150BGI 数据手册

 浏览型号71V67603S150BGI的Datasheet PDF文件第2页浏览型号71V67603S150BGI的Datasheet PDF文件第3页浏览型号71V67603S150BGI的Datasheet PDF文件第4页浏览型号71V67603S150BGI的Datasheet PDF文件第5页浏览型号71V67603S150BGI的Datasheet PDF文件第6页浏览型号71V67603S150BGI的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
IDT71V67603/Z  
IDT71V67803/Z  
3.3VSynchronousSRAMs  
3.3V I/O, Burst Counter  
PipelinedOutputs,SingleCycleDeselect  
Features  
256K x 36/512K x 18. The IDT71V67603/7803 SRAMs contain write,  
data, address and control registers. Internal logic allows the SRAM to  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
the endofthe write cycle.  
256K x 36, 512K x 18 memory configurations  
Supports high system speed:  
– 166MHz 3.5ns clock access time  
– 150MHz 3.8ns clock access time  
– 133MHz 4.2ns clock access time  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67603/7803canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges. The  
orderofthesethreeaddressesaredefinedbytheinternalburstcounter  
andthe LBO inputpin.  
write enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
The IDT71V67603/7803 SRAMs utilize IDT’s latest high-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm100-  
pin thinplasticquadflatpack(TQFP), a119ballgridarray(BGA) and a 165  
fine pitchballgridarray(fBGA).  
Description  
The IDT71V67603/7803 are high-speed SRAMs organized as  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
OE  
GW  
0
, CS  
1
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
BWE  
BW , BW  
(1)  
1
2
, BW  
3
, BW  
4
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O  
0
-I/O31, I/OP1-I/OP4  
DD, VDDQ  
SS  
Data Input / Output  
Core Power, I/O Power  
Ground  
V
Supply  
Supply  
V
N/A  
5310 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67802.  
FEBRUARY 2009  
1
©2007IntegratedDeviceTechnology,Inc.  
DSC-5310/07  

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