Datasheet > 71V6770375PFGI

71V6770375PFGI

更新时间： 2024-11-09 00:23:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	248K
描述
3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

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中文翻译

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数据手册

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71V6770375PFGI 数据手册

◆

256K X 36, 512K X 18

3.3VSynchronousSRAMs

IDT71V67703

IDT71V67903

3.3V I/O, Burst Counter

Flow-ThroughOutputs,SingleCycleDeselect

Features

256K x 36, 512K x 18 memory configurations

Supports fast access times:

◆

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball

grid array (fBGA)

– 7.5ns up to 117MHz clock frequency

– 8.0ns up to 100MHz clock frequency

– 8.5ns up to 87MHz clock frequency

◆

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite

enable (BWE), and byte writes (BWx)

Green parts available see ordering information

Functional Block Diagram

LBO

ADV

INTERNAL

ADDRESS

Sequence

Burst

CEN

256K x 36/

512K x 18-

BIT

MEMORY

ARRAY

CLK

Burst

Logic

18/19

Binary

Counter

ADSC

A0*

A1*

CLR

ADSP

CLK EN

A0,A1

A2 - A18

ADDRESS

A0–A

17/18

36/18

18/19

BWE

Byte 1

Write Register

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

BW4

CS0

Enable

CLK EN

DATA INPUT

Powerdown

OUTPUT

BUFFER

36/18

I/O0

I/OP1–I/OP4

–I/O31

5309 drw 01

DECEMBER 2014

DSC-5309/06

12 3 4 5 6 7...20

中文翻译

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71V6770380PFG	IDT	获取价格	3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect