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71V67702S80PF9 PDF预览

71V67702S80PF9

更新时间： 2024-09-20 10:58:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
23页 985K
描述
TQFP-100, Tray

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中文翻译

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71V67702S80PF9 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TQFP
包装说明：LQFP,针数：100
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：8 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端子数量：100字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX36封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：225座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm

71V67702S80PF9 数据手册

 浏览型号71V67702S80PF9的Datasheet PDF文件第2页浏览型号71V67702S80PF9的Datasheet PDF文件第3页浏览型号71V67702S80PF9的Datasheet PDF文件第4页浏览型号71V67702S80PF9的Datasheet PDF文件第5页浏览型号71V67702S80PF9的Datasheet PDF文件第6页浏览型号71V67702S80PF9的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
2.5V I/O, Burst Counter  
IDT71V67702  
IDT71V67902  
Flow-ThroughOutputs,SingleCycleDeselect  
Features  
◆
data, address and control registers. There are no registers in the data  
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
theendofthewritecycle.  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67702/7902canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
256K x 36, 512K x 18 memory configurations  
◆
Supports fast access times:  
– 7.5ns up to 117MHz clock frequency  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol( ),bytewrite  
◆
◆
enable (  
3.3V core power supply  
Power down controlled by ZZ input  
2.5V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA).  
), and byte writes ( x)  
◆
◆
◆
◆
the same cycle. If burst mode operation is selected (  
=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandthe  
inputpin.  
TheIDT71V67702/7902SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
Description  
The IDT71V67702/7902 are high-speed SRAMs organized as  
256Kx36/512Kx18.TheIDT71V67702/7902SRAMs containwrite,  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
Data Input / Output  
VDD, VDDQ  
VSS  
Core Power, I/O Power  
Ground  
Supply  
Supply  
N/A  
5317 tbl 01  
NOTE:  
1.  
3 and  
4 are not applicable for the IDT71V67902.  
DECEMBER 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5317/08  
1234567...23

中文翻译

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
71V6770375BQG IDT

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
71V6770375BQG8 IDT

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
71V6770375BQGI IDT

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
71V6770375BQGI8 IDT

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
71V6770375PFG IDT

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

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