XRK39653

更新时间： 2024-09-16 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		输出元件
页数	文件大小	规格书
7页	217K
描述
3.3V, 8-OUTPUT ZERO DELAY BUFFER

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数据手册

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XRK39653 数据手册

PRELIMINARY

XRK39653

3.3V, 8-OUTPUT ZERO DELAY BUFFER

FEBRUARY 2006

REV. P1.0.0

XRK39653 GENERAL DESCRIPTION

use. The second is a full bypass mode that has the PLL

and divider operation removed (BYPASS=0). In this mode

the reference clock directly sources the outputs drivers.

The XRK39653 is a low voltage high performance PLL

based zero delay buffer/clock generator designed for high

speed clock distribution applications. It provides 9 low

skew, low jitter outputs ideal for networking, computing and

telecom applications.

FEATURES

• 8 LVCMOS Clock Outputs

The PLL based design allows the 9 outputs (8 clock outputs

and 1 feedback output) to be phase aligned to the input ref-

erence clock. The outputs source LVCMOS compatible lev-

els and can drive 50Ω transmission lines. If series

termination is used, each output can drive up to 2 lines pro-

viding effectively a fanout of 1:16. The XRK39653’s refer-

ence input accepts a LVPECL clock source.

• 1 Feedback Output

• LVPECL reference clock input

• 25-200 MHz input/output frequency range

■ Input/Output range (÷4): 50-125MHz

■ Input/Output range (÷8): 25-62.5MHz

• 150ps max output to output skew

• Two bypass test mode options

• Fully Integrated PLL

• 3.3V Operation

• Pin compatible with MPC9353

For normal operation (PLL used to source the outputs), the

feedback output (QFB) is connected to the feedback input

(FB_IN). The VCO range of operation is 200 to 500MHz.

This means that the input/output ranges are determined by

the divider setting. If ÷4 is used, the input/output range is 50

to 125MHz (high range), if ÷8 is used the input/output range

is 25 to 62.5MHz (low range).

• Industrial temp range: -40°C to +85°C

For testing purposes two PLL bypass modes are provided.

The first simply replaces the PLL output with the reference

clock (PLL_EN=0, BYPASS=1). The dividers are still in

• 32-Lead TQFP Packaging

FIGURE 1. BLOCK DIAGRAM OF THE XRK39653

VDD

QFB

PECL

Ref

÷ 4

PLL

÷ 2

FB_IN

VDD

PLL_EN

VCO_SEL

BYPASS

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7

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