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XRK49911IJ-2F PDF预览

XRK49911IJ-2F

更新时间: 2024-11-02 19:59:39
品牌 Logo 应用领域
艾科嘉 - EXAR 驱动逻辑集成电路
页数 文件大小 规格书
12页 88K
描述
PLL Based Clock Driver, 49911 Series, 8 True Output(s), 0 Inverted Output(s), TTL, PQCC32, GREEN, PLASTIC, LCC-32

XRK49911IJ-2F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFJ包装说明:QCCJ, LDCC32,.5X.6
针数:32Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
系列:49911输入调节:STANDARD
JESD-30 代码:R-PQCC-J32JESD-609代码:e3
长度:14 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.035 A功能数量:1
反相输出次数:端子数量:32
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC32,.5X.6
封装形状:RECTANGULAR封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:3.3 V
Prop。Delay @ Nom-Sup:0.25 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:3.56 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):2.97 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:TTL
温度等级:INDUSTRIAL端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:10
宽度:11.465 mm最小 fmax:110 MHz
Base Number Matches:1

XRK49911IJ-2F 数据手册

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xr  
XRK49911  
3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER  
JUNE 2005  
REV. 1.0.0  
FEATURES  
FUNCTIONAL DESCRIPTION  
3.75- to 110-MHz output operation  
All output pair skew <100 ps typical  
Three skew grades  
The XRK49911 is a 3.3V High-Speed Low-Voltage  
Programmable Skew Clock Buffer. It is intended for  
high-performance computer systems and offers user  
selectable control over system clock functions to  
optimize timing. Eight outputs, arranged in four  
banks, can each drive 50terminated transmission  
lines while delivering minimal and specified output  
skews and full-swing Low Voltage TTL logic levels.  
-2 : tSKEW0<250ps  
-5 : tSKEW0<500ps  
-7 : tSKEW0<700ps  
Each bank (two outputs per bank) can be individually  
selected for one of nine delay or function  
configurations through two dedicated tri-level inputs.  
These outputs are able to lead or lag the CLKIN input  
reference clock by up to 6 time units from their  
nominal “zero” skew position. The integrated PLL  
allows external load and transmission line delay  
effects to be canceled achieving zero delay capability.  
Combining the zero delay capability with the  
selectable output skew functions, output-to-output  
delays of up to 12 time units can be created.  
Selectable output functions  
Skew adjustments of +/- 6tU (up to 18 ns)  
Inverted and non-inverted  
Operation at 1/2 and 1/4 input frequency  
Operation at 2x and 4x input frequency  
Cycle-Cycle Jitter  
< 25 ps (rms)  
< 200 ps (pk-pk)  
The XRK49911’s divide functions (divide-by-two and  
divide-by-four) allow distribution of a low-frequency  
clock that can be multiplied by two or four at the clock  
destination. This feature facilitates clock distribution  
while allowing maximum system clock flexibility.  
Zero input-to-output delay  
50% duty-cycle outputs  
LVTTL outputs drive 50terminated lines  
Operates from a single 3.3V supply  
32-pin PLCC package  
Green packaging  
Lead free lead frame available  
FIGURE 1. BLOCK DIAGRAM OF THE XRK49911  
H
QA0  
QA1  
M
L
Ref  
CLKIN  
PLL  
QB0  
Feedback  
FB_ IN  
QB1  
Bank “SKEW”  
Control  
FSEL*  
QC0  
PLL_BYPASS*  
QC1  
2
2
2
2
SELA[1:0]*  
SELB[1:0]*  
SELC[1:0]*  
SELD[1:0]*  
QD0  
QD1  
* Tri-Level inputs  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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