XRK69772

更新时间： 2024-09-16 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		时钟发生器
页数	文件大小	规格书
12页	312K
描述
1:12 LVCMOS PLL CLOCK GENERATOR

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XRK69772 数据手册

PRELIMINARY

XRK69772

1:12 LVCMOS PLL CLOCK GENERATOR

APRIL 2006

REV.P1.0.0

Bank C clocks. QSYNC then goes high again when the

coincident rising edges of Bank A and Bank C occur. This

feature is used primarily in applications where Bank A and

Bank C are running at different frequencies, and is

particularly useful when they are running at non-integer

multiples of one another.

GENERAL DESCRIPTION

The XRK69772 is a PLL based LVCMOS Clock Generator

targeted for high performance and low skew clock distribu-

tion applications. The XRK69772 can select between one

of three reference inputs and provides 14 LVCMOS outputs

-12 outputs (3 banks of 4) for clock distribution, 1 for feed-

back and 1 for synchronization.

The XRK69772 has an output frequency range of 8.33MHz

to125MHz and an input frequency range of 5MHz to

120MHz.

The XRK69772 is a highly flexible device. It can be config-

ured to accept either a crystal oscillator input or one of two

LVCMOS compatible inputs for use as the input reference

clock source. To support clock redundancy, two LVCMOS

inputs are provided. Switching the internal reference clock

is controlled by the control input, CLK_SEL.

FEATURES

• Fully Integrated PLL

• Selectable crystal oscillator or LVCMOS inputs for

reference clock source

The XRK69772 uses PLL technology to frequency lock its

outputs to the input reference clock. The divider in the feed-

back path will determine the frequency of the VCO. Each of

the separate output banks can individually divide down the

VCO output frequency. This allows the XRK69772 to gen-

erate a multitude of different bank frequency ratios and out-

put-to-input frequency ratios.

• 14 LVCMOS outputs

■ 3 banks with 4 outputs each. Frequencies can

be individually controlled by bank

■ 1 dedicated feedback with frequency control

■ 1 Sync

• VCO Range 200MHz to 480MHz

• Output freq. range: 5MHz to 240MHz

• Max Output Skew of 250ps

• Cycle-to-cycle jitter: 150ps (typ)

APPLICATIONS

The outputs of the XRK69772 can individually be immobi-

lized, in the low state, by use of the stop clock feature. All

outputs except QC0 and QFB can be immobilized through a

2 pin serial interface. Global output disabling and reset can

be achieved the control input MR/OE.

The XRK69772 also has a QSYNC output which can be

used for system synchronization purposes. It monitors

Bank A and Bank C outputs and goes low one period of the

faster clock prior to coincident rising edges of Bank A and

• System Clock generator

• Zero Delay Buffer

PRODUCT ORDERING INFORMATION

PRODUCT NUMBER

XRK69772CR

XRK69772IR

PACKAGE TYPE

52-LEAD LQFP

OPERATING TEMPERATURE RANGE

0°C to +70°C

-40°C to +85°C

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...12

中文翻译

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与XRK69772相关器件

型号	品牌	获取价格	描述	数据表
XRK69772CR	EXAR	获取价格	1:12 LVCMOS PLL CLOCK GENERATOR
XRK69772CV	EXAR	获取价格	Clock Generator, 240MHz, CMOS, PQFP52, 10 X 10 MM, 1.4 MM HEIGHT, LQFP-52
XRK69772IR	EXAR	获取价格	1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773	EXAR	获取价格	1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773CR	EXAR	获取价格	1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773CV	EXAR	获取价格	Clock Generator, 240MHz, CMOS, PQFP52, 10 X 10 MM, 1.4 MM HEIGHT, LQFP-52
XRK69773IR	EXAR	获取价格	1:12 LVCMOS PLL CLOCK GENERATOR
XRK69773IV	EXAR	获取价格	Clock Generator, 240MHz, CMOS, PQFP52, 10 X 10 MM, 1.4 MM HEIGHT, LQFP-52
XRK69774	EXAR	获取价格	1:14 LVCMOS PLL CLOCK GENERATOR
XRK69774CR	EXAR	获取价格	1:14 LVCMOS PLL CLOCK GENERATOR

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