Datasheet > XRK4991ACJ-5

XRK4991ACJ-5

更新时间： 2024-11-02 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		时钟
页数	文件大小	规格书
13页	326K
描述
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

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XRK4991ACJ-5 数据手册

PRELIMINARY

3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER

XRK4991A

FEBRUARY 2005

REV.P1.0.2

at the clock destination. This feature minimizes clock

distribution difficulty while allowing maximum system

clock speed and flexibility.

FUNCTIONAL DESCRIPTION

The XRK4991A 3.3V High-Speed Low-Voltage

Programmable Skew Clock Buffer offers user

selectable control over system clock functions to

optimize the timing of high-performance computer

systems. Eight individual drivers, arranged as four

pairs of user-controllable outputs, can each drive

terminated transmission lines with impedances as

low as 50Ω while delivering minimal and specified

output skews and full-swing logic levels (LVTTL).

FEATURES

• Ref input is 5V tolerant

• 3 pairs of programmable skew outputs

• Low skew: 200ps same pair, 250ps all outputs

• Selectable

positive

negative

edge

synchronization: Excellent for DSP applications

Each output can be hardwired to one of nine delay or

function configurations. Delay increments of 0.7 to

1.5 ns are determined by the operating frequency

with outputs able to skew up to ±6 time units from

their nominal “zero” skew position. The completely

integrated PLL allows external load and transmission

line delay effects to be canceled. When this “zero

delay” capability is combined with the selectable

output skew functions, the user can create output-to-

output delays of up to ±12 time units.

• Synchronous output enable

• Output frequency: 3.75MHz to 85MHz

• 2x, 4x, 1/2, and 1/4 outputs

• 2 skew grades

• 3-level inputs for skew and PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• 32-pin PLCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Green packaging

Divide-by-two and divide-by-four output functions are

provided for additional flexibility in designing complex

clock systems. When combined with the internal PLL,

these divide functions allow distribution of a low-

frequency clock that can be multiplied by two or four

FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A

TEST

FB_IN

PHASE

FREQ

DET

VCO AND TIME

UNIT GENERATOR

FILTER

CLKIN

FSEL

QD0

QD1

SELD0

SELD1

Select Inputs

SKEW

QC0

QC1

SELC0

SELC1

SELECT

QB0

QB1

SELB0

SELB1

MATRIX

QA0

QA1

SELA0

SELA1

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...13

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与XRK4991ACJ-5相关器件

型号	品牌	获取价格	描述	数据表
XRK4991ACJ-7	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991AIJ-5	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991AIJ-7	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991CJ-2	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991CJ-2F	EXAR	获取价格	暂无描述
XRK4991CJ-5	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991CJ-7	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991IJ-2	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4991IJ-5	EXAR	获取价格	3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
XRK4993	EXAR	获取价格	3.3V PROGRAMMABLE SKEW CLOCK BUFFER

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