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XRK32309CDTR-1 PDF预览

XRK32309CDTR-1

更新时间: 2024-09-16 03:13:51
品牌 Logo 应用领域
艾科嘉 - EXAR 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 335K
描述
LOW-COST 3.3V ZERO DELAY BUFFER

XRK32309CDTR-1 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
系列:32309输入调节:STANDARD
JESD-30 代码:R-PDSO-G16长度:9.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:8最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.75 mm子类别:Clock Driver
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mm最小 fmax:120 MHz
Base Number Matches:1

XRK32309CDTR-1 数据手册

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PRELIMINARY  
XRK32309  
LOW-COST 3.3V ZERO DELAY BUFFER  
MAY 2006  
REV.P1.0.1  
In this case, the skew between the outputs of two  
devices is guaranteed to be less than 700 ps.  
GENERAL DESCRIPTION  
FUNCTIONAL DESCRIPTION  
The available versions of XRK32309 are shown in  
Offered in both 16 pin SOIC and TSSOP packages, Table 12, “Ordering Information,” on page 10. The  
XRK32309 is a low cost 3.3V zero delay buffer. It is XRK32309-1 is the base part.  
designed to distribute high speed clocks by taking  
one reference input and driving nine output clocks.  
FEATURES  
The feedback of its on-chip PLL is internally  
10-MHz to 120-MHz operating range, compatible  
connected to the FB output. XRK32309 devices  
operate over 10-100 MHz frequency range with 30 pF  
loads and up to 120MHz with lower loads (10 pF).  
The -1H version has higher drive strength than the  
base -1 version, featuring faster rise and fall time.  
with CPU and PCI bus frequencies  
Zero input-output propagation delay  
Multiple low-skew outputs  
Output-output skew less than 250 ps  
Device-device skew less than 700 ps  
The XRK32309 has two banks each with four  
outputs. These outputs are controlled by two select  
input lines according to the Table 2, “Select Input  
Decoding,” on page 3. In cases where not all outputs  
are needed, bank B can be tri-stated. The select  
lines also enable putting the device in a bypass mode  
where the input is directly applied to the outputs. This  
feature is useful for chip and testing purposes.  
One input drives nine outputs, grouped as 4 +  
4 + 1  
Less than 200 ps cycle-cycle jitter, compatible with  
Pentium -based systems  
Test Mode to bypass phase-locked loop (PLL) (see  
“Select Input Decoding” on page 2)  
Available in space-saving 16-pin 150-mil SOIC or  
Some applications may require distributing the clock  
to several destinations. In such situations, multiple  
XRK32309 devices can be connected to accept the  
same input clock and generate several clock signals.  
4.4-mm TSSOP packages  
3.3V operation  
Industrial and commercial temperature available  
FIGURE 1. BLOCK DIAGRAM OF THE XRK32309  
FB  
PLL  
MUX  
QA0  
QA1  
QA2  
QA3  
QB0  
QB1  
QB2  
QB3  
REF  
S2  
Select Input  
Decoding  
S1  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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