XRK32510

更新时间： 2024-11-02 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		时钟驱动器输出元件
页数	文件大小	规格书
7页	109K
描述
3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS

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数据手册

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XRK32510 数据手册

XRK32510

3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS

OCTOBER 2005

REV. 1.0.1

FEATURES

GENERAL DESCRIPTION

• ^{Spread Spectrum Clock Compatible}

• ^{Operating frequency range: 25MHz to 175MHz}

• ^{Low noise}

• ^{Low jitter internal PLL}

• ^{No external RC filter components required}

The XRK32510 is a high performance, low jitter, low

skew clock driver. The XRK32510 uses phase-lock

loop (PLL) tecnology to synthesize the CLK_IN signal

into 10 output signals (QA), synchronized in both

phase and frequency. XRK32510 features low skew,

low jitter and 50% duty cycle making it a perfect fit in

dual in line memory module (DIMM) board clocking,

PC133 SDRAM designs and other server

applications.

• ^{Meets or exceeds DPC133 registered DIMM}

specification 1.1

• ^{Output Enable (OE) pin can be used to disable the}

The 10 outputs can be disabled using the Output

Enable (OE) pin.

CLCK_OUT pins

• ^{Operating supply of 3.3V VDD}

• ^{Plastic 24 Pin TSSOP package}

By connecting the Feedback Output (FB_OUT) signal

to the Feedback Input (FB_IN) signal, the

propagation delay from CLK_IN to the 10 buffered

Outputs is nearly zero.

FIGURE 1. BLOCK DIAGRAM OF THE XRK32510

FB_OUT

QA0

QA1

QA2

QA3

CLK_IN

FB_IN

Ref

QA4

PLL

QA5

QA6

QA7

QA8

QA9

AVDD

PRODUCT ORDERING INFORMATION

PRODUCT NUMBER

PACKAGE TYPE

OPERATING TEMPERATURE RANGE

XRK32510CG

24 Pin TSSOP

0°C to +70°C

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7

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