XRK32309ID-1

更新时间： 2024-11-02 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
13页	335K
描述
LOW-COST 3.3V ZERO DELAY BUFFER

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中文翻译

获取价格

数据手册

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XRK32309ID-1 数据手册

PRELIMINARY

XRK32309

LOW-COST 3.3V ZERO DELAY BUFFER

MAY 2006

REV.P1.0.1

In this case, the skew between the outputs of two

devices is guaranteed to be less than 700 ps.

GENERAL DESCRIPTION

FUNCTIONAL DESCRIPTION

The available versions of XRK32309 are shown in

Offered in both 16 pin SOIC and TSSOP packages, Table 12, “Ordering Information,” on page 10. The

XRK32309 is a low cost 3.3V zero delay buffer. It is XRK32309-1 is the base part.

designed to distribute high speed clocks by taking

one reference input and driving nine output clocks.

FEATURES

The feedback of its on-chip PLL is internally

• 10-MHz to 120-MHz operating range, compatible

connected to the FB output. XRK32309 devices

operate over 10-100 MHz frequency range with 30 pF

loads and up to 120MHz with lower loads (10 pF).

The -1H version has higher drive strength than the

base -1 version, featuring faster rise and fall time.

with CPU and PCI bus frequencies

• Zero input-output propagation delay

• Multiple low-skew outputs

■ Output-output skew less than 250 ps

■ Device-device skew less than 700 ps

The XRK32309 has two banks each with four

outputs. These outputs are controlled by two select

input lines according to the Table 2, “Select Input

Decoding,” on page 3. In cases where not all outputs

are needed, bank B can be tri-stated. The select

lines also enable putting the device in a bypass mode

where the input is directly applied to the outputs. This

feature is useful for chip and testing purposes.

■ One input drives nine outputs, grouped as 4 +

4 + 1

• Less than 200 ps cycle-cycle jitter, compatible with

Pentium -based systems

• Test Mode to bypass phase-locked loop (PLL) (see

“Select Input Decoding” on page 2)

• Available in space-saving 16-pin 150-mil SOIC or

Some applications may require distributing the clock

to several destinations. In such situations, multiple

XRK32309 devices can be connected to accept the

same input clock and generate several clock signals.

4.4-mm TSSOP packages

• 3.3V operation

• Industrial and commercial temperature available

FIGURE 1. BLOCK DIAGRAM OF THE XRK32309

PLL

MUX

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

REF

Select Input

Decoding

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...13

中文翻译

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与XRK32309ID-1相关器件

型号	品牌	获取价格	描述	数据表
XRK32309ID-1H	EXAR	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
XRK32309IDTR-1	EXAR	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
XRK32309IDTR-1H	EXAR	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
XRK32309IG-1H	EXAR	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
XRK32309IGTR-1H	EXAR	获取价格	LOW-COST 3.3V ZERO DELAY BUFFER
XRK32398IL-1	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32510	EXAR	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
XRK32510CG	EXAR	获取价格	3.3V PHASE-LOCK LOOP CLOCK DRIVER WITH 10 CLOCK OUTPUTS
XRK39351	EXAR	获取价格	3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER
XRK39351_0611	EXAR	获取价格	3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

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