5秒后页面跳转
捷配首页

Datasheet > XC2C384-10TQ144I
XC2C384-10TQ144I PDF预览

XC2C384-10TQ144I

更新时间： 2024-09-19 19:23:35
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
26页 297K
描述
Flash PLD, 10ns, 384-Cell, CMOS, PQFP144, 20 X 20 MM, 0.50 MM PITCH, TQFP-144

阅读下载

中文翻译

获取价格

XC2C384-10TQ144I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP144,.87SQ,20针数：144
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.18其他特性：YES
系统内可编程：YESJESD-30 代码：S-PQFP-G144
JESD-609代码：e0JTAG BST：YES
长度：20 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：118
宏单元数：384端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 118 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装等效代码：QFP144,.87SQ,20封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：225
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：10 ns认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：20 mm
Base Number Matches：1

XC2C384-10TQ144I 数据手册

 浏览型号XC2C384-10TQ144I的Datasheet PDF文件第2页浏览型号XC2C384-10TQ144I的Datasheet PDF文件第3页浏览型号XC2C384-10TQ144I的Datasheet PDF文件第4页浏览型号XC2C384-10TQ144I的Datasheet PDF文件第5页浏览型号XC2C384-10TQ144I的Datasheet PDF文件第6页浏览型号XC2C384-10TQ144I的Datasheet PDF文件第7页 
0
R
XC2C384 CoolRunner-II CPLD  
0
0
DS095 (v3.2) March 8, 2007  
Product Specification  
Features  
Description  
•
Optimized for 1.8V systems  
The CoolRunner-II 384-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
-
-
As fast as 7.1 ns pin-to-pin delays  
As low as 14 μA quiescent current  
•
•
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
This device consists of twenty four Function Blocks  
inter-connected by a low power Advanced Interconnect  
Matrix (AIM). The AIM feeds 40 true and complement inputs  
to each Function Block. The Function Blocks consist of a 40  
by 56 P-term PLA and 16 macrocells which contain numer-  
ous configuration bits that allow for combinational or regis-  
tered modes of operation.  
Available in multiple package options  
-
-
-
-
-
144-pin TQFP with 118 user I/O  
208-pin PQFP with 173 user I/O  
256-ball FT (1.0mm) BGA with 212 user I/O  
324-ball FG (1.0mm) BGA with 240 user I/O  
Pb-free available for all packages  
•
Advanced system features  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt-trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as direct input registers to store signals directly  
from input pins.  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Unsurpassed low power management  
·
-
-
-
·
DataGATE enable (DGE) signal control  
-
-
-
Four separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (divide by 2,4,6,8,10,12,14,16)  
CoolCLOCK  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
-
-
Advanced design security  
PLA architecture  
·
·
Superior pinout retention  
100% product term routability across function  
block  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on  
selected I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
Circuitry has also been included to divide one externally  
supplied global clock (GCK2) by eight different selections.  
This yields divide by even and odd clock frequencies.  
-
-
The use of the clock divide (division by 2) and DualEDGE  
flip-flop gives the resultant CoolCLOCK feature.  
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility  
-
Hot pluggable  
DataGATE is a method to selectively disable inputs of the  
CPLD that are not of interest during certain points in time.  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
© 2002--2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS095 (v3.2) March 8, 2007  
www.xilinx.com  
1
Product Specification  
1234567...26

中文翻译

下载PDF

XC2C384-10TQ144I 替代型号

型号 品牌 替代类型 描述 数据表
XC2C384-10TQ144C XILINX

完全替代

 暂无描述
XC2C384-7TQG144C XILINX

完全替代

 Flash PLD, 7.5ns, 384-Cell, CMOS, PQFP144, 20 X 20 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144

与XC2C384-10TQ144I相关器件

型号 品牌 获取价格 描述 数据表
XC2C384-10TQG144C XILINX

获取价格

 		暂无描述
XC2C384-10TQG144I XILINX

获取价格

 		暂无描述
XC2C384-7FGG324C XILINX

获取价格

 		Flash PLD, 7.5ns, 384-Cell, CMOS, PBGA324, 23 X 23 MM, 1 MM PITCH, LEAD FREE, FBGA-324
XC2C384-7FT256C XILINX

获取价格

 		暂无描述
XC2C384-7PQ208C XILINX

获取价格

 		暂无描述
XC2C384-7TQG144C XILINX

获取价格

 		Flash PLD, 7.5ns, 384-Cell, CMOS, PQFP144, 20 X 20 MM, 0.50 MM PITCH, LEAD FREE, TQFP-144
XC2C512 XILINX

获取价格

 		CoolRunner-II CPLD Family
XC2C512-10FG324I XILINX

获取价格

 		暂无描述
XC2C512-10FGG324C XILINX

获取价格

 		Flash PLD, 10ns, 512-Cell, CMOS, PBGA324, 23 X 23 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FBGA
XC2C512-10FTG256I XILINX

获取价格

 		Flash PLD, 10ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FTBG

与XC2C384-10TQ144I相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证