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XC2C512-7FG324C

更新时间： 2024-11-08 21:07:47
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XC2C512-7FG324C 数据手册

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0
R
CoolRunner-II CPLD Family  
0
0
DS090 (v3.1) September 11, 2008  
Product Specification  
-
-
SSTL2_1,SSTL3_1, and HSTL_1 on 128  
macrocell and denser devices  
Hot pluggable  
Features  
•
•
•
Optimized for 1.8V systems  
-
-
Industry’s fastest low power CPLD  
Densities from 32 to 512 macrocells  
•
•
PLA architecture  
-
-
Wide package availability including fine pitch:  
-
Superior pinout retention  
100% product term routability across function block  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
Chip Scale Package (CSP) BGA, Fine Line BGA,  
TQFP, PQFP, VQFP, and QFN packages  
Pb-free available for all packages  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
-
·
•
•
•
Design entry/verification using Xilinx and industry  
standard CAE tools  
-
-
-
-
-
On-The-Fly Reconfiguration (OTF)  
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt trigger input (per pin)  
Multiple I/O banks on all devices  
Free software support for all densities using Xilinx®  
WebPACK™ tool  
Industry leading nonvolatile 0.18 micron CMOS  
process  
Unsurpassed low power management  
·
DataGATE external signal control  
-
Flexible clocking modes  
-
-
Guaranteed 1,000 program/erase cycles  
Guaranteed 20 year data retention  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (÷ 2,4,6,8,10,12,14,16)  
CoolCLOCK  
Family Overview  
-
Global signal options with macrocell control  
Xilinx CoolRunner™-II CPLDs deliver the high speed and  
ease of use associated with the XC9500/XL/XV CPLD fam-  
ily with the extremely low power versatility of the XPLA3  
family in a single CPLD. This means that the exact same  
parts can be used for high-speed data communications/  
computing systems and leading edge portable products,  
with the added benefit of In System Programming. Low  
power consumption and high-speed operation are com-  
bined into a single family that is easy to use and cost effec-  
tive. Clocking techniques and other power saving features  
extend the users’ power budget. The design features are  
supported starting with Xilinx ISE® 4.1i WebPACK tool.  
Additional details can be found in Further Reading,  
page 14.  
·
Multiple global clocks with phase selection per  
macrocell  
Multiple global output enables  
Global set/reset  
·
·
-
-
Abundant product term clocks, output enables and  
set/resets  
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on select  
I/O pins  
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels on all parts  
-
-
-
Table 1 shows the macrocell capacity and key timing  
parameters for the CoolRunner-II CPLD family.  
-
-
Table 1: CoolRunner-II CPLD Family Parameters  
XC2C32A  
32  
XC2C64A  
64  
XC2C128  
128  
XC2C256  
256  
XC2C384  
384  
XC2C512  
512  
Macrocells  
Max I/O  
33  
64  
100  
184  
240  
270  
T
T
T
F
(ns)  
(ns)  
(ns)  
3.8  
4.6  
5.7  
5.7  
7.1  
7.1  
PD  
SU  
CO  
1.9  
2.0  
2.4  
2.4  
2.9  
2.6  
3.7  
3.9  
4.2  
4.5  
5.8  
5.8  
(MHz)  
323  
263  
244  
256  
217  
179  
SYSTEM1  
© 2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS090 (v3.1) September 11, 2008  
www.xilinx.com  
1
Product Specification  
1234567...16

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XC2C512-7FG324C 替代型号

型号 品牌 替代类型 描述 数据表
XC2C512-10FG324I XILINX

完全替代

 暂无描述
XC2C512-10FGG324C XILINX

完全替代

 Flash PLD, 10ns, 512-Cell, CMOS, PBGA324, 23 X 23 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FBGA

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 		Flash PLD, 7.5ns, 512-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, FTB
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